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DM74S373 * DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
August 1986 Revised May 2000
DM74S373 * DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74S373 are transparent D-type latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74S374 are edge-triggered Dtype flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.
Features
s Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P input reduce D-C loading on data lines
Ordering Code:
Order Number DM74S373WM DM74S373N DM74S374WM DM74S374N Package Number M20B N20A M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
DM74S373N
DM74S374N
(c) 2000 Fairchild Semiconductor Corporation
DS006486
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DM74S373 * DM74S374
Truth Tables
DM74S373 Output Control L L L H Enable G H H L X H L X X H L Q0 Z D Output Output Control L L L H L X H L X X H L Q0 Z DM74S374 Clock D Output
H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don't Care Z = High Impedance State = Transition from LOW-to-HIGH level, Q0 = The level of the output before steady-state input conditions were established.
Logic Diagrams
74S373 Transparent Latches 74S374 Positive-Edge-Triggered Flip-Flops
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DM74S373 * DM74S374
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
DM74S373 Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL tW tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width (Note 2) Pulse Width (Note 3) Data Setup Time (Note 4)(Note 5) Data Hold Time (Note 4)(Note 5) Free Air Operating Temperature Enable HIGH Enable LOW Enable HIGH Enable LOW 6 7.3 15 15 0 10 0 70 Parameter Min 4.75 2 0.8 -6.5 20 Nom 5 Max 5.25 Units V V V mA mA ns ns ns ns ns C
Note 2: CL = 15 pF, RL = 280, TA = 25C and VCC = 5V. Note 3: CL = 50 pF and RL = 280, TA = 25C and VCC = 5V. Note 4: The symbol () indicates the falling edge of the clock pulse is used for reference. Note 5: TA = 25C and VCC = 5V.
DM74S373 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOZH IOZL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage HIGH Level Input Current LOW Level Input Current Off-State Output Current with Off-State Output Current with Short Circuit Output Current Supply Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max, VI = 2.7V VCC = Max, VI = 0.5V VCC = Max, VO = 2.4V VCC = Max, VO = 0.5V VCC = Max (Note 7) VCC = Max Outputs HIGH or LOW Outputs Disabled
Note 6: All typicals are at VCC = 5V, TA = 25C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Min
Typ (Note 6)
Max -1.2
Units V V
2.4
3.2 0.5 1 50 -250 50 -50
V mA A A A A mA mA
Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
HIGH Level Output Voltage Applied VIH = Min, VIL = Max LOW Level Output Voltage Applied VIH = Min, VIL = Max -40 105
-100 160 190
3
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DM74S373 * DM74S374
DM74S373 Switching Characteristics
at VCC = 5V and TA = 25C RL = 280 Symbol Parameter From (Input) To (Output) tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time to HIGH Level Output (Note 8) Output Disable Time to LOW Level Output (Note 8)
Note 8: CL = 5 pF
CL = 15 pF Min Max 12 12 14 18 15 18 9 12
CL = 50 pF Min Max 14 16 14 21 17 23
Units
Data to Any Q Data to Any Q Enable to Any Q Enable to Any Q Output Control to Any Q Output Control to Any Q Output Control to Any Q Output Control to Any Q
ns ns ns ns ns ns ns ns
DM74S374 Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 9) Clock Frequency (Note 10) Pulse Width (Note 9) Pulse Width (Note 10) tSU tH TA Clock HIGH Clock LOW Clock HIGH Clock LOW 0 0 6 7.3 15 15 5 2 0 70 ns ns C ns 0.8 -6.5 20 75 75 Parameter Min 4.75 Nom 5 Max 5.25 Units V V V mA mA MHz MHz
Data Setup Time (Note 11)(Note 12) Data Hold Time (Note 11)(Note 12) Free Air Operating Temperature
Note 9: CL = 15 pF, R L = 280, TA = 25C and VCC = 5V. Note 10: CL = 50 pF, RL = 280, TA = 25C and VCC = 5V. Note 11: The symbol () indicates the rising edge of the clock pulse is used for reference. Note 12: TA = 25C and VCC = 5V.
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DM74S373 * DM74S374
DM74S374 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted) Symbol VI VOH VOL II IH IIL IOZH IOZL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Off-State Output Current with HIGH Level Output Voltage Applied Off-State Output Current with LOW Level Output Voltage Applied Short Circuit Output Current Supply Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max, VI = 5.5V VCC = Max, VI = 2.7V VCC = Max, VI = 0.5V VCC = Max, VO = 2.4V VIH = Min, VIL = Max VCC = Max, VO = 0.5V VIH = Min, VIL = Max VCC = Max (Note 14) VCC = Max Outputs HIGH Outputs LOW Outputs Disabled
Note 13: All typicals are at VCC = 5V, TA = 25C. Note 14: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Min
Typ (Note 13)
Max -1.2
Units V V
2.4
3.2 0.5 1 50 -250 50
V mA A A A
-50 -40 90 -100 110 140 160
A mA mA
DM74S374 Switching Characteristics
at VCC = 5V and TA = 25C RL = 280 Symbol Parameter From (Input) To (Output) fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output (Note 15) Output Disable Time from LOW Level Output (Note 15)
Note 15: CL = 5 pF
CL = 15 pF Min Max 75
CL = 50 pF Min Max 75 15 20 17 23
Units
MHz ns ns ns ns ns ns
Clock to Any Q Clock to Any Q Output Control to Any Q Output Control to Any Q Output Control to Any Q Output Control to Any Q
15 17 15 18 9 12
5
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DM74S373 * DM74S374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
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DM74S373 * DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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